The invention relates to a semi-conductor module and to a method and a system for producing this type of semi-conductor module.
As mobile electronics become more and more significant, conventional printed circuit boards with active or passive components, such as semi-conductor chips, applied to them two-dimensionally are becoming less significant. The electric or electronic components are stacked three-dimensionally. The aim here is to stack as many chips as possible in the form of a “stack” within the height of an individual housing. This technology is supported by very thin wafers which are being produced to be better and better. If the material thicknesses of thinned wafers—and so also of the individual silicon sheets—came within the range of over 150 μm in the past, material thicknesses of below 50 μm are currently possible.
This development also corresponds to the legality known as Moore's law according to which the electronics in semi-conductors are being constantly reduced in size. The production and stacking of these thin chips is a consequent development of these attempts to accommodate as many functions as possible over the smallest possible area within a single semi-conductor module. If in the past many functions have been accommodated two-dimensionally on boards, attempts are now being made to accommodate as many of these chips as possible in the smallest possible volume—and so three-dimensionally. Therefore, the person skilled in the art speaks of 3-dimensional integration.
Until now these thin chips have been stacked and contacted with one another by means of the classical wire bond. Here a thin metallic wire is fitted between the individual contacts of the chips and so connect the chips to one another electrically. However, this form of wiring has proven to be very intricate and defective.
As a result silicone through-contacting, also called the TSV process, has gained in significance. Here the thin wafer is perforated by means of continuous microholes between the layers of an integrated circuit—a so-called via—which can be in the form of etched or drilled holes. These vias are filled metallically and so contacts from the front side to the rear side of the wafer and so also of the resulting chips are produced. The challenge now is to generate from the contacts of a bottom chip electrical contacting to the contacts of the rear side of a chip stacked on the latter. At the same time, however, the two chips must be isolated electrically from one another over the rest of the surface.
It can be understood from DRAM chips how this object is currently achieved. With DRAM chips there is the requirement to produce as much storage space as possible within a small volume. With some manufacturers a so-called interposer—as a wiring plane—is introduced between the components to be stacked. This is facilitated by the chips all having the same function and the same geometric design. By means of the design it is therefore possible for the contact surface of a chip lying at the bottom to be located in the precise position where the contact surface is also positioned on the rear side of the chip lying at the top. The respective counter piece of a contact is therefore always located exactly opposite, and this facilitates contacting.
A thinned wafer, which is through-contacted in the same way as the vias of the TSV process at the points provided and connects the contact surfaces of both chips to one another electrically, is also used here in many cases as an interposer. This thin wafer is then introduced between the bottom and the top wafer and guides the electric signals. For the purpose of better contactability a metallic elevation can also be applied here either on the contact surfaces of the bottom and/or on the rear side of the top wafer. Such elevations are also called “bumps” by the person skilled in the art. It is also possible, however, to apply these bumps to one or to both sides of the interposer. For the purpose of permanent contacting the bumps should in many cases fuse onto the respective opposite contact surface and produce a permanent metallic connection.
However, contacting by means of bumps is prone to error. The desired electric contactings are often only produced in insufficient quantity. Furthermore, the thermal contacting between the semi-conductor chips and the interposer is not optimal for most applications. The heat dissipation from the chips to the interposer can often not be guaranteed sufficiently by the bumps.
While it is relative easy according to the prior art to stack components of the same type and geometric design and to contact them with one another, this is very much harder with different components because the latter can not be configured for this, or only to an insufficient extent, as regards design. As the number of different chips within a stack increases, the latter also becomes increasingly heavier. Additional problems also occur here because contacts between two different chips have to be rewired and lines may also cross here.
By means of an interposer according to the prior art this can be partially resolved by conductor paths being applied to both sides of this thin wafer, thus allowing relatively flexible contacts to be displaced geometrically. This method is very complex, however, and requires corresponding lithographic methods and so mostly also expensive masks. Therefore, it can not be adapted very easily and with an increasing number of chips stacked one above the other becomes very expensive. Due to the high mask costs the method can generally only be considered for semi-conductor modules which are produced in large numbers.
Furthermore, it is a problem that whole wafers always have to be stacked here. Only after the wafers have been stacked are the latter diced by sawing in order to obtain the individual semi-conductor modules. This makes it difficult to stack at the very least chips of different types and sizes. One must anticipate considerable wastage here, and this raises the cost of each functioning semi-conductor module.
Due to the current necessity for stacking on a wafer plane, the shape and size of the chips to be stacked is currently designed exactly uniform. Otherwise separation, for example by means of sawing, would no longer be possible because at least one chip would no longer correspond to the sawing model here.
Moreover, problems arise from the fact that in the production of wafers the chips located over the latter do not all have the desired properties and totally fail here or only have limited functionality. Therefore the yield on one wafer is now very rarely 100%. If one now stacks two wafers, the yield of which is respectively below 100%, it is more or less inevitable that a good chip will be placed here over or beneath a bad chip. In this way the yield of good semiconductor modules is affected very negatively.